FIG. 1 shows a standard prior art totem pole power amplifier. Two power switches or power transistors 11 and 12 are connected together between two power supplies or between two poles, V(+) and V(-), of a bipolar power supply, 21 and 22, respectively. Transistors 11 and 12 turn on and off in response to control circuitry 5 which modifies an input signal. Transistors 11 and 12 can be NPN, PNP, MOSFET, IGT, or any combination thereof. Transistor 11 supplies or sources current to load 15 whereas transistor 12 removes or sinks current from load 15. The totem pole configuration is used whenever a bipolar output current is required.
The circuit shown in FIG. 1 can be operated in the switch mode (i.e. pulse width modulated) or in the amplifier mode (i.e. linear region). A typical prior art circuit for operating a totem pole power amplifier in the switch mode is shown in FIG. 2 where a digital pulse width modulated input signal 55, typically with a duration of 200 .mu.sec, is fed to the circuit to activate transistors 11 and 12. The control circuitry consists of turn-on delays 63 and 64 and output drivers 60 and 61. Turn-on delay 60 delays the propogation of the positive going input pulse by some fixed amount of time. Typically, this fixed delay is 10 to 20 .mu.sec. After the fixed delay, the small input signal triggers output driver 60 which enables a large output current 16 to be supplied to load 15 through transistor 11. Turn-on delay circuit 64 operates in a similar manner to turn-on delay circuit 63 except that it delays the propogation of the negative going input pulse which is inverted by inverter 65. Turnon delays 63 and 64 are necessary to compensate for the storage time delay in transistors 11 and 12. Typically, turn-on delays 63 and 64 are fixed at the same value.
When input signal 55 triggers a change in the operation of transistors 11 and 12 from sinking current 17 to sourcing current 16, current 17 will continue to flow for some short period of time T since load 15 is typically inductive. The time period T is defined as: EQU T=ts+tf
where ts =storage time and tf =current fall time. The turn-on delay time T(on) of turn-on delays 63 and 64 must be at least as long as the maximum time T during which current will continue to flow after transistor 12 has been turned off. Thus, T(on) .gtoreq. T or T(on) .gtoreq. ts +tf.
The storage time ts of a power transistor or, for that matter, any transistor varies with respect to the collector current. The larger the collector current, the longer the storage time ts. T(on) must be selected for the worst case situation where ts is the longest storage time that possibly can be experienced by transistors 11 and 12. This selection, however, leads to exaggerated turn-on delays when the storage time is at a minimum. Additionally, this fixed time delay limits the bandwidth of the input signal by limiting how frequently transistors 11 and 12 can be turned on and off.
The circuit shown in FIG. 2 for implementing a fixed time delay is an open-loop circuit since no feedback from transistors 11 and 12 is utilized. An open-loop system, however, creates the danger of catastrophic failure. If, for example, one of the transistors 11 or 12 were to fail, which is not uncommon, the time delay and driver circuits, unaware of the failure, would proceed to turn on the opposite transistor in response to the input signal causing stress in that device and, potentially, causing a catastrophic failure.
One way to determine if failure has occurred is to monitor the state of the transistors. FIG. 3 shows a prior art measuring circuit of a monitoring device for determining whether transistor 11 is in saturation or whether transistor 11 is off and diode 13 is on. A floating power supply, modeled as a voltage supply 25 and a source resistance 27 is attached to the collector and emitter of transistor 11. Current 18 is measured to determine if transistor 11 is in saturation. If current 18 is flowing, transistor 11 is supposed to be in saturation. Diode 35 protects the floating supply when the collector to emitter voltage of transistor 11 is quite large (i.e. .vertline.V(+)+V(-).vertline.) such as when transistor 11 is not in saturation.
If the monitoring device senses that current 18 is flowing, a signal will be sent indicating that transistor 11 is in saturation. However, a false signal can be sent if transistor 11 is not in the saturation condition but is off and diode 13 is on, i.e. freewheeling. In this case a negative voltage appears across the collector-emitter of transistor 11 and current 18 will flow through the path indicated by arrows 18, 19 and 19a. This false signal, of course, will slow down any response which is waiting for the transistor to turn off and go out of saturation. A more accurate monitoring device is needed, which does not give an improper "in saturation" signal.
There is a need for a time delay circuit which overcomes the problems of the prior art open-loop turn-on delays, namely, exaggerated turn-on delay times for most output conditions and no output feedback to prevent further failure and which overcomes the problems of the prior art feed back monitors, namely, an inaccurate signal.